Modern processors, and in fact all synchronous logic circuits use a clock to control execution of the circuit. The speed of this clock, which in large part determines how quickly the processor runs applications, is traditionally limited by worst case delay. That is, the clock must be slow enough to give the circuit the maximum time it will need to execute correctly, also called its propagation delay. However, this delay cannot be determined precisely because of three main factors. First, when computer chips are produced, manufacturing induced variations create variable delays in the chips. Second, during operation, variations in environmental conditions such as temperature and voltage affect the delay through the circuit. Finally, although it is possible to find the longest paths through the logic, it is not known how often the input combinations given during operation will use these paths. To avoid timing errors, traditional design assumes worst case values for these factors, giving an overly high delay estimate, and causing the clock period to be set too low.
The main limitation that this solution overcomes is the worst case delay assumption that places a minimum on the clock period of modern digital circuits. Overcoming this assumption allows circuits, such as superscalar or pipelined processors, to run at a much higher speed.
Despite numerous efforts have been made to enhance processor performance, problems remain.